An associative storage memory is a device which is capable of indicating whether retrieved information is stored in it. When the information stored matches the retrieval information then the contents of an associated memory are read out. FIG. 1 shows an example of prior art associative storage memory which has a plurality of information retrieval words 170, 170, . . . , 170. These information retrieval words 170 correspond to respective words 172, 172, . . . , 172 of separately provided RAM's. Information identifying the stored contents of the respective RAM words 172 is stored in the respective corresponding associative storage memory words 170. When retrieval information is applied to the retrieval words 170, stored in the corresponding RAM word corresponds to that retrieval information is read out.
Each of the information retrieval words 170 comprises a plurality of memory cells 174. One memory cell 174 is shown in detail in FIG. 2. Each memory cell 174 includes an information hold circuit 180 which comprises a flip-flop circuit formed by two inverters 182 and 184 each having its input connected to the output of the other. The input of the inverter 182 and the output of the inverter 184 are connected to a bit line 188 through the source-drain conduction path of an N-channel MOS transistor 186 which acts as a transfer gate. Similarly, the input of the inverter 184 and the output of the inverter 182 are connected to a bit line 192 through the source-drain conduction path of an N-channel MOS transistor 190 which acts as a transmission gate. The gates of the MOS transistors 186 and 190 are connected to a word line 194.
The memory cell 174 also includes a retrieval circuit 196. The retrieval circuit 196 includes N-channel MOS transistors 200 and 202 having their source-drain conduction paths connected in series with each other between a match line 198 and a ground potential point. The gate of the transistor 200 is connected to the bit line 188, and the gate of the transistor 202 is connected to the the input of the inverter 184 and to the output of the inverter 182. The retrieval circuit 196 also includes N-channel MOS transistors 204 and 206 having their source-drain conduction paths connected in series between the match line 198 and and ground potential point. The gate of the transistor 204 is connected to the bit line 192, and the gate of the transistor 206 is connected to the input of the inverter 182 and to the output of the inverter 184.
When stored information is read out from the memory cell 174, the bit lines 188 and 192 are first precharged to a high level (e.g. a certain supply potential), and then, the word line 194 is set to the high level to render the transmission gates 186 and 190 conductive. This places the bit line 188 at a level corresponding to an output of the inverter 184 and also places the bit line 192 at a level corresponding to an output of the inverter 182.
When information is written to the memory cell 174, the bit lines 188 and 192 are first precharged to the high level, and, after that, the word line 194 is placed at the high level, which renders the transmission gates 186 and 190 conductive. Thereafter, the bit line 188 is placed at the level of information to be stored, with the bit line 192 placed at the opposite level.
For retrieving information from the memory cell 174, the bit lines 188 and 192 are first precharged to a low level (e.g. ground potential), and, after that, the match line 198 is charged to the high level. To determine if the low level is stored in the information hold circuit 180, the bit lines 188 and 192 are placed at the low and high levels, respectively. Assuming that the voltage level of the output of the inverter 184 corresponds to the stored information of the information hold circuit 180 and low level information is actually stored in the information hold circuit 180, the transistor 202 is conductive, the transistor 206 is non-conductive, and the match line 198 is maintained at the high level. On the other hand, if the stored information of the circuit 180 is at a high voltage level, the transistor 206 is conductive, while the transistor 202 is non-conductive since the output of the inverter 182 is at the low level. Since the bit line 192 is at the high level, the transistor 204 is also conductive. Accordingly, the match line 198 is at the low level. In other words, if the retrieval information matches the stored information, the match line 198 is maintained at the high level, whereas it is placed at the low level if the retrieval information and the stored information do not match.
Referring to in FIGS. 1 and 2, since the retrieval circuits 196 of the respective memory cells 174 of each word 170 are connected in common to the match line 198, the match line 198 is maintained high only when retrieval information applied via the respective bit lines 188 and 192 to each of the memory cell 174 in that word 170 matches information stored in that memory cell 174 for all of the memory cells 174. If match line 198 stays high, the stored information in a word of a RAM to which the matchline 198 maintained at the high level is connected is read out.
Since N-channel MOS transistors are used as transmission gates, the bit lines 188 and 192 are precharged to the supply potential prior to writing or reading to and from the respective memory cells 174, which enables reliable reading and writing operations at a high speed, as is known in the art. Further, the reason why the bit lines 188 and 192 are precharged to the low level prior to retrieval operation is as follows. When the match line 198 is precharged to the high level, the gate of one of the transistors 202 and 206 is necessarily at the high level because the output of either one of the inverters 182 and 184 is necessarily at the high level. Then, if both bit lines 188 and 192 are at the high level, both transistors 200 and 204 becomes conductive, whereby a conduction path is provided either by the transistor 200, 202 or the transistor 204, 206 between the match line 198 and a reference potential point. In that case the match line 198 cannot be precharged to the high level, or even if it can be, significant power will be wasted to accomplish the precharging. This is the reason why the bit lines 188 and 198 are precharged to the low level prior to the retrieval operation.
As described above, with the memory cell described above, the bit lines 188 and 192 must be precharged to the high level prior to performing a read/write operation with respect to the cell. The also the bit lines 188 and 192 must be precharged to the low level prior to the retrieval operation. In other words, each time the memory cell changes its operating mode, the bit lines 188 and 192 must be precharged to the high or low level, which, in turn, necessarily requires power and time for the precharging. This prevents such devices from operating with lower power and at higher speed.
Assume that a memory cell which can operate with a low power and at a high speed can be realized, such improvement will be cancelled if other elements constituting the associative storage memory operate with large power and at low speed. It is, therefore, desirable that such elements can also operate at low power and high speed.
An object of the present invention is to provide an associative storage memory of which memory cells are capable of operating with reduced power consumption and at a high speed.
Another object of the present invention is to provide an associative storage memory in which elements forming the associative storage memory with memory cells operate with reduced power consumption and at a high speed.